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Fix abs Operator int accuracy issue #31920

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Merged
merged 2 commits into from
Sep 3, 2025
Merged

Fix abs Operator int accuracy issue #31920

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d603917
Fix int32 abs precision loss
sgbihu Sep 1, 2025
7a4f91c
Add Abs tests
sgbihu Sep 1, 2025
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15 changes: 0 additions & 15 deletions src/plugins/intel_cpu/src/emitters/plugin/x64/jit_dnnl_ext_emitters.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -85,21 +85,6 @@ class jit_elu_emitter : public jit_dnnl_emitter {
}
};

class jit_abs_emitter : public jit_dnnl_emitter {
public:
jit_abs_emitter(dnnl::impl::cpu::x64::jit_generator_t* host,
dnnl::impl::cpu::x64::cpu_isa_t host_isa,
const std::shared_ptr<ov::Node>& n,
ov::element::Type exec_prc = ov::element::f32)
: jit_dnnl_emitter(host, host_isa, n, exec_prc) {
kind = dnnl_eltwise_abs;
alpha = 0.F;
beta = 0.F;

set_injector();
}
};

class jit_clamp_emitter : public jit_dnnl_emitter {
public:
jit_clamp_emitter(dnnl::impl::cpu::x64::jit_generator_t* host,
Expand Down
71 changes: 71 additions & 0 deletions src/plugins/intel_cpu/src/emitters/plugin/x64/jit_eltwise_emitters.cpp
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Expand Up @@ -2852,4 +2852,75 @@ void jit_bitwise_xor_emitter::emit_isa(const std::vector<size_t>& in_vec_idxs,
h->uni_vxorps(vmm_dst, vmm_src0, vmm_src1);
}

/// ABS ///
jit_abs_emitter::jit_abs_emitter(x64::jit_generator_t* host,
x64::cpu_isa_t host_isa,
const std::shared_ptr<ov::Node>& node)
: jit_emitter(host, host_isa, get_arithmetic_binary_exec_precision(node)) {
prepare_table();
}

jit_abs_emitter::jit_abs_emitter(x64::jit_generator_t* host, x64::cpu_isa_t host_isa, ov::element::Type exec_prc)
: jit_emitter(host, host_isa, exec_prc) {
prepare_table();
}

size_t jit_abs_emitter::get_inputs_num() const {
return 1;
}

void jit_abs_emitter::emit_impl(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const {
if (host_isa_ == x64::sse41) {
emit_isa<x64::sse41>(in_vec_idxs, out_vec_idxs);
} else if (host_isa_ == x64::avx2) {
emit_isa<x64::avx2>(in_vec_idxs, out_vec_idxs);
} else if (host_isa_ == x64::avx512_core) {
emit_isa<x64::avx512_core>(in_vec_idxs, out_vec_idxs);
} else {
OV_CPU_JIT_EMITTER_THROW("Unsupported ISA ", host_isa_);
}
}

template <x64::cpu_isa_t isa>
void jit_abs_emitter::emit_isa(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const {
using Vmm = typename conditional3<isa == x64::sse41, Xmm, isa == x64::avx2, Ymm, Zmm>::type;
auto vmm_src = Vmm(in_vec_idxs[0]);
auto vmm_dst = Vmm(out_vec_idxs[0]);

auto uni_vpabsd = [this](Vmm vmm_dst, Vmm vmm_src) {
switch (exec_prc_) {
case ov::element::f32:
h->uni_vandps(vmm_dst, vmm_src, table_val("positive_mask"));
break;
case ov::element::i32:
if (isa == x64::sse41) {
h->pabsd(vmm_dst, vmm_src);
} else if (any_of(host_isa_, x64::avx2, x64::avx512_core)) {
h->vpabsd(vmm_dst, vmm_src);
} else {
OV_CPU_JIT_EMITTER_THROW("Unsupported ISA ", host_isa_);
}
break;
default:
OV_CPU_JIT_EMITTER_THROW("Unsupported precision");
}
};

if (isa == x64::sse41) {
h->uni_vmovups(vmm_dst, vmm_src);
uni_vpabsd(vmm_dst, vmm_dst);
} else {
uni_vpabsd(vmm_dst, vmm_src);
}
}

std::set<std::vector<element::Type>> jit_abs_emitter::get_supported_precisions(
[[maybe_unused]] const std::shared_ptr<ov::Node>& node) {
return {{element::f32}, {element::i32}};
}

void jit_abs_emitter::register_table_entries() {
push_arg_entry_of("positive_mask", 0x7fffffff, true);
}

} // namespace ov::intel_cpu
21 changes: 21 additions & 0 deletions src/plugins/intel_cpu/src/emitters/plugin/x64/jit_eltwise_emitters.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -933,4 +933,25 @@ class jit_bitwise_xor_emitter : public jit_emitter {
void emit_isa(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const;
};

class jit_abs_emitter : public jit_emitter {
public:
jit_abs_emitter(dnnl::impl::cpu::x64::jit_generator_t* host,
dnnl::impl::cpu::x64::cpu_isa_t host_isa,
ov::element::Type exec_prc = ov::element::f32);
jit_abs_emitter(dnnl::impl::cpu::x64::jit_generator_t* host,
dnnl::impl::cpu::x64::cpu_isa_t host_isa,
const std::shared_ptr<ov::Node>& n);

size_t get_inputs_num() const override;
static std::set<std::vector<element::Type>> get_supported_precisions(
const std::shared_ptr<ov::Node>& node = nullptr);

private:
void emit_impl(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const override;

template <dnnl::impl::cpu::x64::cpu_isa_t isa>
void emit_isa(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const;
void register_table_entries() override;
};

} // namespace ov::intel_cpu
4 changes: 2 additions & 2 deletions src/plugins/intel_cpu/src/nodes/kernels/x64/jit_uni_eltwise_generic.cpp
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Expand Up @@ -395,7 +395,7 @@ std::shared_ptr<jit_emitter> jit_uni_eltwise_generic<isa>::create_eltwise_emitte
OV_CASE(Algorithm::EltwiseElu, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseTanh, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseSigmoid, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseAbs, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseAbs, jit_abs_emitter),
OV_CASE(Algorithm::EltwiseSqrt, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseSoftRelu, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseClamp, jit_dnnl_aux_emitter),
Expand Down Expand Up @@ -888,7 +888,7 @@ std::set<std::vector<element::Type>> eltwise_precision_helper::get_supported_pre
OV_CASE(Algorithm::EltwiseElu, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseTanh, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseSigmoid, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseAbs, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseAbs, jit_abs_emitter),
OV_CASE(Algorithm::EltwiseSqrt, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseSoftRelu, jit_dnnl_aux_emitter),
OV_CASE(Algorithm::EltwiseClamp, jit_dnnl_aux_emitter),
Expand Down
1 change: 1 addition & 0 deletions ...ugins/intel_cpu/tests/functional/shared_tests_instances/single_layer_tests/activation.cpp
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Expand Up @@ -63,6 +63,7 @@ const std::map<ActivationTypes, std::vector<std::vector<float>>> activationTypes

// List of operations that should be tested also with integer precision
const std::map<ActivationTypes, std::vector<std::vector<float>>> intActivationTypes = {
{ActivationTypes::Abs, {}},
{ActivationTypes::Acosh, {}},
{ActivationTypes::Asinh, {}},
{ActivationTypes::Atan, {}},
Expand Down
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