Pinned Loading

1. UVM-Based-AXI-Memory-Verification-System UVM-Based-AXI-Memory-Verification-System Public

   This project implements an AXI4 slave in SystemVerilog with a UVM-based testbench. It features driver, monitor, agent, sequences, and multiple test scenarios to verify burst read/write operations, …

   Jupyter Notebook

2. AXI4-Lite-GPIO-Perpherial-with-Interrupts-and-Debouncing AXI4-Lite-GPIO-Perpherial-with-Interrupts-and-Debouncing Public

   SystemVerilog 1

3. Modulation_Qsys_Nios_SystemVerilog Modulation_Qsys_Nios_SystemVerilog Public

   Implemented Direct Digital Synthesis (DDS) and displayed ASK, BPSK, FSK, and LFSR waveforms on a VGA-connected monitor. Controlled FSK modulation dynamically through the Nios II processor.

   SystemVerilog

4. Multi-Core-RC4-Code-Breaking Multi-Core-RC4-Code-Breaking Public

   RC4 is a stream cipher that was once widely used for encrypting web traffic and other data transmissions. Although it is now considered insecure and has been replaced by more robust algorithms, RC4…

   SystemVerilog