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AmirhosseinPooladAmirhosseinPoolad
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Add interposer regression test
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‎libs/libarchfpga/src/read_xml_arch_file_interposer.cpp‎

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@@ -25,7 +25,7 @@ t_interposer_cut_inf parse_interposer_cut_tag(pugi::xml_node interposer_cut_tag,
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pugiutil::expect_only_children(interposer_cut_tag, {"interdie_wire"}, loc_data);
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for (pugi::xml_node interdie_wire_tag : interposer_cut_tag.children()) {
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const std::vector<std::string> interdie_wire_attributes = {{"sg", "sg_link", "offset_start", "offset_end", "offset_increment", "num"}};
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const std::vector<std::string> interdie_wire_attributes = {{"sg_name", "sg_link", "offset_start", "offset_end", "offset_increment", "num"}};
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pugiutil::expect_only_attributes(interdie_wire_tag, interdie_wire_attributes, loc_data);
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t_interdie_wire_inf interdie_wire;

‎vtr_flow/arch/interposer/k6_N10_40nm_interposer.xml‎

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<!--
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Architecture with no fracturable LUTs
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- 40 nm technology
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- General purpose logic block:
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K = 6, N = 10
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- Routing architecture: L = 4, fc_in = 0.15, fc_out = 0.15
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- Unidirectional (mux-based) routing
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Details on Modelling:
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Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. This architecture has no fracturable LUTs nor any heterogeneous blocks.
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The delays and areas are based on a mix of values from commercial 40 nm
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FPGAs with a comparable architecture and 40 nm interconnect and
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transistor models.
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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-->
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<architecture>
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<!--
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ODIN II specific config begins
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This part of the architecture file describes the "primitives"
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that exist in a device to the synthesis tool used to "elaborate"
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verilog into these primitives (which is called ODIN-II).
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Basic LUTs, I/Os and FFs are built into the language used by this
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flow (blif keywords .names, .input, .output and .latch), so they
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don't have to be described here.
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For this lab you are also given the benchmark netlists after
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synthesis is complete (in the blif directory), so you don't need
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to run ODIN II.
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-->
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<models>
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</models>
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<!-- ODIN II specific config ends -->
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<!-- Descritions of the physical tiles that exist on the die begins -->
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<tiles>
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<tile name="io" area="0">
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<sub_tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io" pin_mapping="direct"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/>
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<!-- IOs go on the periphery of the FPGA in this
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architecture. Since I don't want to define four
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different physical I/Os for the left, right, top,
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and bottom sides just say each pin of the I/O
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block is accessible from all four sides so we can
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reach routing channels on some side of the block
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no matter which side of the chip we're on.
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-->
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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<!-- Define general purpose logic block (CLB) begin -->
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<!-- Area below is for everything inside the
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logic block (LUTs, FFs, intra-cluster
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routing). It's a bit on the low side given the large crossbars in this
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architecture - more appropriate for a lower-cost
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FPGA with smaller transistors and narrower metal.
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-->
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<tile name="clb" area="18000">
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<!-- We can place a clustered block of type clb on a tile location
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of type clb.
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-->
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<sub_tile name="clb">
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<equivalent_sites>
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<site pb_type="clb" pin_mapping="direct"/>
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</equivalent_sites>
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<!-- We have a full crossbar between the cluster inputs and the
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LUT inputs, so the router can route to *any* input or from
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*any* output on the logic block. Hence mark the logic block
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inputs as fully logically equivalent (swappable by the router) and also the
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logic block outputs as logically equivalent, which means
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they can also be swapped by the router.
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-->
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="10" equivalent="instance"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/>
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<pinlocations pattern="spread"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- Physical tile descriptions end -->
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<!-- Chip layout (in terms of where tiles are) begins -->
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<layout>
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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<fixed_layout name="vtr_homogeneous_extra_small" width="10" height="10">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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<interposer_cut dim="x" loc="5">
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<interdie_wire sg_name="interposer_sg" sg_link="L_UP" offset_start="0" offset_end="0" offset_increment="0" num="30"/>
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<interdie_wire sg_name="interposer_sg" sg_link="L_DOWN" offset_start="0" offset_end="0" offset_increment="0" num="30"/>
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</interposer_cut>
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</fixed_layout>
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</layout>
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<!-- Chip layout ends -->
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<!-- Electrical and inter-cluster (general) routing description begins -->
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<device>
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<!-- Some area and timing parameters -->
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
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area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
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-->
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<area grid_logic_tile_area="0"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<!-- Define the switch block pattern (pattern of switches between inter-tile routing wires)
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The Wilton switch block is a sample pattern; you can use custom switch blocks for more control -->
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<switch_block type="wilton" fs="3"/>
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<!-- Set which switch to use for input connection blocks. Only affects timing and area, not connectivity -->
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
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book area formula. This means the mux transistors are about 5x minimum drive strength.
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We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
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mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage.
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-->
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
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Wires of this pitch will fit over a 90 nm
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high logic tile (which is about the height of a Stratix IV logic tile).
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I'm using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square.
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length below is in units of logic blocks, and Rmetal and Cmetal are
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per logic block passed, so wire delay adapts automatically if you change the
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length=? value. -->
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<!-- Currently only one type of routing wire, which
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is of length 4 and has switches to every connection
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box (4 of them) and switch box (5 of them)
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it passes. You can change wirelengths just by changing the length="?" values
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and changing the number of 1's (or 0's) in the <sb type and <cb type lines to
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match the number of switch blocks and connection blocks a wire of that length
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would span. -->
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<segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<!-- Electrical and inter-cluster routing description ends -->
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<!-- Description of the capabilities (number of BLEs, modes) and local interconnect in
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each type of complex (clustered) block (e.g. LBs) begins
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-->
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<complexblocklist>
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<!-- Define I/O pads begin -->
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<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<!-- IOs can operate as either inputs or outputs.
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The delays below are to and from registers in the I/O (and generally I/Os are registered
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today).
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-->
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<!-- Not modeling I/O power for now -->
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<power method="ignore"/>
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</pb_type>
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<!-- Define I/O pads ends -->
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<!-- Define general purpose logic block (CLB) begin -->
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<!-- Area below is for everything inside the
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logic block (LUTs, FFs, intra-cluster
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routing).
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-->
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<pb_type name="clb">
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="10" equivalent="instance"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe basic logic element.
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Each basic logic element has a 6-LUT that can be optionally registered
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-->
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- 6-LUT mode definition begin -->
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<mode name="n1_lut6">
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<!-- Define 6-LUT mode -->
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<pb_type name="ble6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define LUT -->
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<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="6" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<!-- These are the delay per LUT input on a Stratix IV LUT.
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The average is 261 ps, and inputs earlier in the mux tree are slower.
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-->
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<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
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82e-12
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173e-12
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261e-12
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263e-12
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398e-12
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397e-12
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<!-- many lines below to describe the interconnect
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wires, muxes and crossbars inside a cluster.
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-->
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<interconnect>
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<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
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<direct name="direct2" input="lut6.out" output="ff.D">
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<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
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<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
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</direct>
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<direct name="direct3" input="ble6.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="ble6.in"/>
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<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
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<direct name="direct3" input="fle.clk" output="ble6.clk"/>
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</interconnect>
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</mode>
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<!-- 6-LUT mode definition end -->
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</pb_type>
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<interconnect>
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<!-- We use a full crossbar to get logical equivalence at inputs of CLB
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The delays below come from Stratix IV. the delay through a connection block
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input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
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delay on the connection block input mux (modeled by Ian Kuon), so the remaining
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delay within the crossbar is 95 ps.
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The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
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Since all our outputs LUT outputs go to a BLE output, and have a delay of
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25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
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to get the part that should be marked on the crossbar. -->
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<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
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<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
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<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[9:0].clk">
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</complete>
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<!-- The BLE outputs are directly connected to the
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CLB (cluster) outputs.
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-->
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<direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
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</interconnect>
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</pb_type>
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<!-- Define general purpose logic block (CLB) ends -->
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</complexblocklist>
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<power>
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<local_interconnect C_wire="2.5e-10"/>
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<mux_transistor_size mux_transistor_size="3"/>
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<FF_size FF_size="4"/>
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<LUT_transistor_size LUT_transistor_size="4"/>
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</power>
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<clocks>
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<clock buffer_size="auto" C_wire="2.5e-10"/>
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</clocks>
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<scatter_gather_list>
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<sg_pattern name="interposer_sg" type="unidir">
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<gather>
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<wireconn num_conns="30" from_type="wire" from_switchpoint="1" side="rltb"/>
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</gather>
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<scatter>
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<wireconn num_conns="30" to_type="wire" to_switchpoint="0" side="rtl"/>
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</scatter>
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<sg_link_list>
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<sg_link name="L_UP" y_offset="1" mux="sw" seg_type="wire"/>
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<sg_link name="L_DOWN" y_offset="-1" mux="sw" seg_type="wire"/>
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</sg_link_list>
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</sg_pattern>
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</scatter_gather_list>
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</architecture>

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_interposer/config/config.txt‎

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##############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/verilog
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# Path to directory of architectures to use
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archs_dir=arch/interposer
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# Add circuits to list to sweep
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circuit_list_add=ch_intrinsics.v
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# Add architectures to list to sweep
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arch_list_add=k6_N10_40nm_interposer.xml
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# Use a fixed size device
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circuit_constraint_list_add=(ch_intrinsics.v, device=vtr_homogeneous_extra_small)
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# Parse info and how to parse
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parse_file=vpr_standard.txt
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# How to parse QoR info
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qor_parse_file=qor_standard.txt
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# Pass requirements
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pass_requirements_file=pass_requirements.txt
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# Script parameters
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script_params_common = -track_memory_usage

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_interposer/config/golden_results.txt‎

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k6_N10_40nm_interposer.xml ch_intrinsics.v common 1.39 vpr 63.27 MiB -1 -1 0.24 32920 3 0.07 -1 -1 37056 -1 -1 25 99 -1 -1 success v8.0.0-13909-g0298a690c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 15.2.1 on Linux-6.14.9-300.fc42.x86_64 x86_64 2025-09-19T15:59:53 betzgrp-pcamir.eecg /home/amirpoolad/Dev/vtr-verilog-to-routing/vtr_flow/scripts 64792 99 130 342 472 1 225 254 10 10 100 -1 vtr_homogeneous_extra_small 23.6 MiB 0.06 1395.83 666 26786 4334 19176 3276 63.3 MiB 0.05 0.00 2.06334 1.99047 -111.451 -1.99047 1.99047 0.05 0.000410201 0.000382142 0.0164063 0.0152932 -1 -1 -1 -1 30 1038 11 1.152e+06 450000 194421. 1944.21 0.40 0.139057 0.127114 6972 36796 -1 905 11 476 757 28868 8304 1.89907 1.89907 -121.629 -1.89907 0 0 238537. 2385.37 0.01 0.02 0.02 -1 -1 0.01 0.0143138 0.0133681

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