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loglav03loglav03
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Moved top module list to benchmarks folder and explicitly use top modules in yosys hierarchy passes
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+103
-78
lines changed

5 files changed

+103
-78
lines changed

‎vtr_flow/benchmarks/top_modules.tcl

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,75 @@
1+
namespace eval ::slang {
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# INFO: Maps HDL files to respective top module(s)
3+
# top_map insertion syntax:
4+
# <file> <top module>
5+
array set top_map {
6+
and_latch.v and_latch
7+
multiclock_output_and_latch.v multiclock_output_and_latch
8+
multiclock_reader_writer.v multiclock_reader_writer
9+
multiclock_separate_and_latch.v multiclock_separate_and_latch
10+
arm_core.v arm_core
11+
bgm.v bgm
12+
blob_merge.v RLE_BlobMerging
13+
boundtop.v paj_boundtop_hierarchy_no_mem
14+
ch_intrinsics.v memset
15+
diffeq1.v diffeq_paj_convert
16+
diffeq2.v diffeq_f_systemC
17+
LU8PEEng.v LU8PEEng
18+
LU32PEEng.v LU32PEEng
19+
LU64PEEng.v LU64PEEng
20+
mcml.v mcml
21+
mkDelayWorker32B.v mkDelayWorker32B
22+
mkPktMerge.v mkPktMerge
23+
mkSMAdapter4B.v mkSMAdapter4B
24+
or1200.v or1200_flat
25+
raygentop.v paj_raygentop_hierarchy_no_mem
26+
sha.v sha1
27+
stereovision0.v sv_chip0_hierarchy_no_mem
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stereovision1.v sv_chip1_hierarchy_no_mem
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stereovision2.v sv_chip2_hierarchy_no_mem
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stereovision3.v sv_chip3_hierarchy_no_mem
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button_controller.sv top
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display_control.sv top
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debounce.sv top
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timer.sv top
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deepfreeze.style1.sv top
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pulse_led.v top
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clock.sv top
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single_ff.v top
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single_wire.v top
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PWM.v top
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flattened_pulse_width_led.sv top
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modify_count.sv top
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time_counter.sv top
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spree.v system
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attention_layer.v attention_layer
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bnn.v bnn
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tpu_like.small.os.v top
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tpu_like.small.ws.v top
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dla_like.small.v DLA
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conv_layer_hls.v top
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conv_layer.v conv_layer
52+
eltwise_layer.v eltwise_layer
53+
robot_rl.v robot_maze
54+
reduction_layer.v reduction_layer
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spmv.v spmv
56+
softmax.v softmax
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test.v top
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mult_9x9.v mult_nxn
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mult_8x8.v mult_nxn
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mult_7x7.v mult_nxn
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mult_6x6.v mult_nxn
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mult_5x5.v mult_nxn
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mult_4x4.v mult_nxn
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mm3.v mm3
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d_flip_flop.v d_flip_flop
66+
}
67+
# INFO: List of HDL includes files
68+
# includes_map insertion syntax:
69+
# <file> include
70+
array set includes_map {
71+
hard_block_include.v include
72+
complex_dsp_include.v include
73+
hard_mem_include.v include
74+
}
75+
}

‎vtr_flow/misc/yosys/slang_filelist.tcl

Lines changed: 11 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -7,71 +7,10 @@
77

88

99
namespace eval ::slang {
10-
# INFO: Maps HDL files to respective top module(s)
11-
# top_map insertion syntax:
12-
# <file> <top module>
13-
array set top_map {
14-
and_latch.v and_latch
15-
multiclock_output_and_latch.v multiclock_output_and_latch
16-
multiclock_reader_writer.v multiclock_reader_writer
17-
multiclock_separate_and_latch.v multiclock_separate_and_latch
18-
arm_core.v arm_core
19-
bgm.v bgm
20-
blob_merge.v RLE_BlobMerging
21-
boundtop.v paj_boundtop_hierarchy_no_mem
22-
ch_intrinsics.v memset
23-
diffeq1.v diffeq_paj_convert
24-
diffeq2.v diffeq_f_systemC
25-
LU8PEEng.v LU8PEEng
26-
LU32PEEng.v LU32PEEng
27-
LU64PEEng.v LU64PEEng
28-
mcml.v mcml
29-
mkDelayWorker32B.v mkDelayWorker32B
30-
mkPktMerge.v mkPktMerge
31-
mkSMAdapter4B.v mkSMAdapter4B
32-
or1200.v or1200_flat
33-
raygentop.v paj_raygentop_hierarchy_no_mem
34-
sha.v sha1
35-
stereovision0.v sv_chip0_hierarchy_no_mem
36-
stereovision1.v sv_chip1_hierarchy_no_mem
37-
stereovision2.v sv_chip2_hierarchy_no_mem
38-
stereovision3.v sv_chip3_hierarchy_no_mem
39-
button_controller.sv top
40-
display_control.sv top
41-
debounce.sv top
42-
timer.sv top
43-
deepfreeze.style1.sv top
44-
pulse_led.v top
45-
clock.sv top
46-
single_ff.v top
47-
single_wire.v top
48-
PWM.v top
49-
flattened_pulse_width_led.sv top
50-
modify_count.sv top
51-
time_counter.sv top
52-
spree.v system
53-
attention_layer.v attention_layer
54-
bnn.v bnn
55-
tpu_like.small.os.v top
56-
tpu_like.small.ws.v top
57-
dla_like.small.v DLA
58-
conv_layer_hls.v top
59-
conv_layer.v conv_layer
60-
eltwise_layer.v eltwise_layer
61-
robot_rl.v robot_maze
62-
reduction_layer.v reduction_layer
63-
spmv.v spmv
64-
softmax.v softmax
65-
}
66-
# INFO: List of HDL includes files
67-
# includes_map insertion syntax:
68-
# <file> include
69-
array set includes_map {
70-
hard_block_include.v include
71-
}
7210

7311

74-
variable top_args {}
12+
variable top_mods_slang {}
13+
variable top_mods_verilog {}
7514

7615
# Function - build_filelist:
7716
#
@@ -85,11 +24,14 @@ namespace eval ::slang {
8524
# file_list - text file being written to that will contain
8625
# the names of circuits from circuit list.
8726
#
88-
proc build_filelist { circuit_list file_list } {
89-
variable top_args
27+
proc build_filelist { circuit_list file_list tops_path} {
28+
variable top_mods_slang
29+
variable top_mods_verilog
9030
variable top_map
9131
variable includes_map
92-
set top_args {}
32+
source [file join [pwd] "$tops_path"]
33+
set top_mods_slang {}
34+
set top_mods_verilog {}
9335
set fh [open $file_list "w"]
9436
foreach f $circuit_list {
9537
set ext [string tolower [file extension $f]]
@@ -105,7 +47,8 @@ namespace eval ::slang {
10547
} else {
10648
puts $fh $f
10749
set top_name $top_map($f)
108-
lappend top_args --top $top_name
50+
lappend top_mods_slang --top $top_name
51+
lappend top_mods_verilog -top $top_name
10952
}
11053
}
11154
} else {
@@ -114,6 +57,6 @@ namespace eval ::slang {
11457
}
11558
}
11659
close $fh
117-
return $top_args
60+
return [list $top_mods_slang $top_mods_verilog]
11861
}
11962
}

‎vtr_flow/misc/yosys/synthesis.tcl

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -28,16 +28,20 @@ if {$env(PARSER) == "slang" } {
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2929
parmys_arch -a QQQ
3030

31+
variable HDL_tops
32+
33+
# Create a file list containing the name(s) of file(s) \
34+
# to read together with read_slang
35+
source [file join [pwd] "slang_filelist.tcl"]
36+
set readfile [file join [pwd] "filelist.txt"]
37+
#Writing names of circuit files to file list
38+
set HDL_tops [::slang::build_filelist {XXX} $readfile $env(TOPS)]
39+
lassign $HDL_tops top_mods_slang top_mods_verilog
40+
3141
if {$env(PARSER) == "slang" } {
32-
# Create a file list containing the name(s) of file(s) \
33-
# to read together with read_slang
34-
source [file join [pwd] "slang_filelist.tcl"]
35-
set readfile [file join [pwd] "filelist.txt"]
36-
#Writing names of circuit files to file list
37-
set slang_tops [::slang::build_filelist {XXX} $readfile]
3842
puts "Using Yosys read_slang command"
3943
#Read vtr_primitives library and user design verilog in same command
40-
read_slang -v $env(PRIMITIVES) {*}$slang_tops -C $readfile
44+
read_slang -v $env(PRIMITIVES) {*}$top_mods_slang -C $readfile
4145
} elseif {$env(PARSER) == "default" } {
4246
puts "Using Yosys read_verilog command"
4347
read_verilog -nomem2reg +/parmys/vtr_primitives.v
@@ -53,7 +57,8 @@ scc -select
5357
select -assert-none %
5458
select -clear
5559

56-
hierarchy -check -auto-top -purge_lib
60+
#hierarchy -check -auto-top -purge_lib
61+
hierarchy -check {*}$top_mods_verilog -purge_lib
5762

5863
opt_expr
5964
opt_clean
@@ -97,6 +102,7 @@ opt -fast -noff
97102

98103
stat
99104

100-
hierarchy -check -auto-top -purge_lib
105+
#hierarchy -check -auto-top -purge_lib
106+
hierarchy -check {*}$top_mods_verilog -purge_lib
101107

102108
write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ

‎vtr_flow/scripts/python_libs/vtr/parmys/parmys.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,7 @@ def run(
252252
if parmys_args["parser"] in YOSYS_PARSERS:
253253
os.environ["PARSER"] = parmys_args["parser"]
254254
os.environ["PRIMITIVES"] = str(vtr.paths.vtr_primitives_path)
255+
os.environ["TOPS"] = str(vtr.paths.HDL_top_mods_path)
255256
del parmys_args["parser"]
256257
else:
257258
raise vtr.VtrError(

‎vtr_flow/scripts/python_libs/vtr/paths.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
# VTR Paths
99
vtr_flow_path = root_path / "vtr_flow"
1010
vtr_primitives_path = root_path / "build" / "share" / "yosys" / "parmys" / "vtr_primitives.v"
11-
11+
HDL_top_mods_path = root_path / "vtr_flow" / "benchmarks" / "top_modules.tcl"
1212
# ODIN paths
1313
odin_path = root_path / "odin_ii"
1414
odin_exe_path = odin_path / "odin_ii"

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