Is there a way to export the store content? test.v: ```verilog module test (a, b, c); input a, b; output c; assign c = a | b; endmodule ``` ``` cirkit> read_verilog --xmg test.v cirkit [xmg]> show --silent out (out is an empty file) cirkit [xmg]> print --xmg (empty line) ```